METHOD OF MEASURING MISALIGNMENT OF CHIPS, A METHOD OF FABRICATING A FAN-OUT PANEL LEVEL PACKAGE USING THE SAME, AND A FAN-OUT PANEL LEVEL PACKAGE FABRICATED THEREBY

A method of measuring misalignment of chips, a method of fabricating a fan-out panel level package using the same, and a fan-out panel level package fabricated thereby are provided. The measuring method may include obtaining images by scanning chips on a substrate, obtaining absolute offsets of refe...

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Bibliographic Details
Main Authors YANG Yusin, SOHN Younghoon
Format Patent
LanguageEnglish
Published 25.01.2018
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MEASURING
MEASURING ANGLES
MEASURING AREAS
MEASURING ELECTRIC VARIABLES
MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
MEASURING LENGTH, THICKNESS OR SIMILAR LINEARDIMENSIONS
MEASURING MAGNETIC VARIABLES
PHYSICS
SEMICONDUCTOR DEVICES
TESTING
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Summary:A method of measuring misalignment of chips, a method of fabricating a fan-out panel level package using the same, and a fan-out panel level package fabricated thereby are provided. The measuring method may include obtaining images by scanning chips on a substrate, obtaining absolute offsets of reference chips with respect to the substrate in the images, obtaining relative offsets of subordinate chips with respect to the reference chips in the images, and calculating misalignments of the chips based on the absolute offsets and the relative offsets.
Bibliography:Application Number: US201715584166