MEMORY DEVICE WITH IMPROVED LATENCY AND OPERATING METHOD THEREOF

Disclosed is a memory device which includes a first memory cell connected to a word line and a first bit line, a second memory cell connected to the word line and a second bit line, and a row decoder selecting the word line, a row decoder configured to select the word line, and a column decoder. A f...

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Bibliographic Details
Main Authors KIM CHANKYUNG, CHA SOO-HO, PARK SUNGCHUL, CHOE KWANGCHOL
Format Patent
LanguageEnglish
Published 21.12.2017
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:Disclosed is a memory device which includes a first memory cell connected to a word line and a first bit line, a second memory cell connected to the word line and a second bit line, and a row decoder selecting the word line, a row decoder configured to select the word line, and a column decoder. A first distance between the row decoder and the first memory cell is shorter than a second distance between the row decoder and the second memory cell. The column decoder selects the first bit line based on a time point when the first memory cell is activated.
Bibliography:Application Number: US201715599819