PROTECTION OF HIGH-K DIELECTRIC DURING RELIABILITY ANNEAL ON NANOSHEET STRUCTURES

A starting structure for forming a gate-all-around field effect transistor (FET) and a method of fabricating the gate-all-around FET. The method includes forming a stack of silicon nanosheets above a substrateforming an interfacial layer over the nanosheets depositing a high-k dielectric layer confo...

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Bibliographic Details
Main Authors Sankarapandian Muthumanickam, Narayanan Vijay, Loubet Nicolas J, Mehta Sanjay C
Format Patent
LanguageEnglish
Published 09.11.2017
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A starting structure for forming a gate-all-around field effect transistor (FET) and a method of fabricating the gate-all-around FET. The method includes forming a stack of silicon nanosheets above a substrateforming an interfacial layer over the nanosheets depositing a high-k dielectric layer conformally on the interfacial layer. The method also includes depositing a layer of silicon nitride (SiN) above the high-k dielectric layer and performing reliability anneal after depositing the layer of SiN to crystallize the high-k dielectric layer.
Bibliography:Application Number: US201615146325