METHOD OF FORMING A PATTERN FOR INTERCONNECTION LINES AND ASSOCIATED CONTINUITY BLOCKS IN AN INTEGRATED CIRCUIT

A method for forming a pattern for interconnection lines and associated continuity dielectric blocks in an integrated circuit includes providing a structure having a mandrel layer disposed over an etch mask layer, the etch mask layer being disposed over a pattern layer and the pattern layer being di...

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Bibliographic Details
Main Authors CHILD, JR. Craig Michael, STEPHENS Jason Eugene, KIM Byoung Youp, BOUCHE Guillaume
Format Patent
LanguageEnglish
Published 28.09.2017
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A method for forming a pattern for interconnection lines and associated continuity dielectric blocks in an integrated circuit includes providing a structure having a mandrel layer disposed over an etch mask layer, the etch mask layer being disposed over a pattern layer and the pattern layer being disposed over a dielectric stack. Patterning an array of mandrels in the mandrel layer. Selectively etching a beta trench entirely in a mandrel of the array, the beta trench overlaying a beta block mask portion of the pattern layer. Selectively etching a gamma trench entirely in the etch mask layer, the gamma trench overlaying a gamma block mask portion of the pattern layer. Selectively etching the structure to form a pattern in the pattern layer, the pattern including the gamma and beta block mask portions.
Bibliography:Application Number: US201615077480