METHOD FOR PARAMETER EXTRACTION OF A SEMICONDUCTOR DEVICE
A method is provided for parameter extraction of a semiconductor device with a multi-finger gate. The method includes measuring gate-to-source and gate-to-drain capacitances and performing 3D simulation to compute fringing capacitances, thereby computing an overlap capacitance between the gate and a...
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Main Authors | , |
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Format | Patent |
Language | English |
Published |
24.08.2017
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Subjects | |
Online Access | Get full text |
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Summary: | A method is provided for parameter extraction of a semiconductor device with a multi-finger gate. The method includes measuring gate-to-source and gate-to-drain capacitances and performing 3D simulation to compute fringing capacitances, thereby computing an overlap capacitance between the gate and a source/drain extension region, and computing a length of the source/drain extension region according to the overlap capacitance. |
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Bibliography: | Application Number: US201615351626 |