Method for Forming Alignment Marks and Structure of Same

A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. T...

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Main Authors Hsu Kai-Chun, Hsu Tzu-Hsuan, Ting Shyh-Fann, Chou Cheng-Hsien, Tseng Hsiao-Hui, Hsu Wei-Cheng, Tu Yeur-Luen, Lai Chih-Yu, Wang Ching-Chun, Chen Sheng-Chau, Yaung Dun-Nian, Chang Chun-Wei, Chou Shih Pei
Format Patent
LanguageEnglish
Published 20.07.2017
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.
Bibliography:Application Number: US201715477971