SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a semiconductive substrate including a first surface and a second surface opposite to the first surface, a shallow trench isolation (STI) including a first portion at least partially disposed within the semiconductive substrate and tapered from the first surface to...

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Main Authors LU JIECH-FUN, WEN CHI-YUAN, HSUEH CHE-HSIANG, WU MINGI, YEH YU-LUNG, WU JIAN, FANG CHUNIEH, SU CHINGUNG
Format Patent
LanguageEnglish
Published 06.07.2017
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Abstract A semiconductor structure includes a semiconductive substrate including a first surface and a second surface opposite to the first surface, a shallow trench isolation (STI) including a first portion at least partially disposed within the semiconductive substrate and tapered from the first surface towards the second surface, and a second portion disposed inside the semiconductive substrate, coupled with the first portion and extended from the first portion towards the second surface, and a void enclosed by the STI, wherein the void is at least partially disposed within the second portion of the STI.
AbstractList A semiconductor structure includes a semiconductive substrate including a first surface and a second surface opposite to the first surface, a shallow trench isolation (STI) including a first portion at least partially disposed within the semiconductive substrate and tapered from the first surface towards the second surface, and a second portion disposed inside the semiconductive substrate, coupled with the first portion and extended from the first portion towards the second surface, and a void enclosed by the STI, wherein the void is at least partially disposed within the second portion of the STI.
Author WU MINGI
LU JIECH-FUN
WU JIAN
HSUEH CHE-HSIANG
WEN CHI-YUAN
FANG CHUNIEH
YEH YU-LUNG
SU CHINGUNG
Author_xml – fullname: LU JIECH-FUN
– fullname: WEN CHI-YUAN
– fullname: HSUEH CHE-HSIANG
– fullname: WU MINGI
– fullname: YEH YU-LUNG
– fullname: WU JIAN
– fullname: FANG CHUNIEH
– fullname: SU CHINGUNG
BookMark eNrjYmDJy89L5WSwCHb19XT293MJdQ7xD1IIDgkCMkKDXBUc_VwUfB39Qt0cQXxPP3cFX9cQD38XhRAP1yBXfzceBta0xJziVF4ozc2g7OYa4uyhm1qQH59aXJCYnJqXWhIfGmxkYGhuaGliaGngaGhMnCoATJArmg
ContentType Patent
DBID EVB
DatabaseName esp@cenet
DatabaseTitleList
Database_xml – sequence: 1
  dbid: EVB
  name: esp@cenet
  url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP
  sourceTypes: Open Access Repository
DeliveryMethod fulltext_linktorsrc
Discipline Medicine
Chemistry
Sciences
ExternalDocumentID US2017194190A1
GroupedDBID EVB
ID FETCH-epo_espacenet_US2017194190A13
IEDL.DBID EVB
IngestDate Fri Jul 19 15:48:56 EDT 2024
IsOpenAccess true
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-epo_espacenet_US2017194190A13
Notes Application Number: US201615088126
OpenAccessLink https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170706&DB=EPODOC&CC=US&NR=2017194190A1
ParticipantIDs epo_espacenet_US2017194190A1
PublicationCentury 2000
PublicationDate 20170706
PublicationDateYYYYMMDD 2017-07-06
PublicationDate_xml – month: 07
  year: 2017
  text: 20170706
  day: 06
PublicationDecade 2010
PublicationYear 2017
RelatedCompanies TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD
RelatedCompanies_xml – name: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD
Score 3.0946646
Snippet A semiconductor structure includes a semiconductive substrate including a first surface and a second surface opposite to the first surface, a shallow trench...
SourceID epo
SourceType Open Access Repository
SubjectTerms BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Title SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
URI https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170706&DB=EPODOC&locale=&CC=US&NR=2017194190A1
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3dS8MwED_GFPVNp-LHlILSt2K3dV37UKRrUqvQdrSN7G2sbQqCdMNV_Pe9hE73tLd8wJEc-eXul-QuAI9jZDiGVSHSKm5rhjGstKXNTY1bS6MsqoFRyqQ-YWQGzHibj-cd-NzGwsg8oT8yOSIiqkC8N3K_Xv8fYhH5tnLzlH9g0-rZzxyitux4MMEVbKpk6tBZTGJP9TyHpWqUyD7k62j-XORKB-hITwQe6PtUxKWsd42KfwqHM5RXN2fQ4XUPjr3t32s9OArbK28stujbnIOVCqXFEWFeFidKmiVYYAlV3IgooRsx3xX11-hFCWkWxETJAprQ2L-AB59mXqDhEBZ_M16wdHe8o0vo1quaX4EyynPb5kO9zJHHFIVuWzlHF01fituU0uLX0N8n6WZ_9y2ciKp8jWr2odt8ffM7tLlNfi9V9QsEvn-s
link.rule.ids 230,309,783,888,25576,76876
linkProvider European Patent Office
linkToHtml http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3dS8MwED_GFOebTsWPqQWlb8V9dF37MKRrUjtd09GmsrextikI0g1X8d_3Gjbd096SHITLkV_ufvm4ADz2keHoZo5Iy4Wl6Xo31xaWMDRhLvQszTt6JpP6-MzwYv111p_V4HP7FkbmCf2RyRERUSnivZTr9ep_E4vIu5Xrp-QDm5bPLh8SdcOOOwOcwYZKRkM6DUjgqI4zjCOVhVKGfB3dn41c6QCD7EGFB_o-qt6lrHadinsCh1PsryhPoSaKJjSc7d9rTTjyN0feWNygb30GZlQZLWAkdngQKhEPsRCHVLEZUXybxa5d1cfsRfEp9wKicI-GNHDP4cGl3PE0VGH-N-J5HO3q27uAerEsxCUovSSxLNFtZwnymDRtW2YiMERrL6rTlMwUV9Da19P1fvE9NDzuT-aTMXu7geNKJG-mGi2ol1_f4hb9b5ncSbP9Aizlgp8
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=SEMICONDUCTOR+STRUCTURE+AND+MANUFACTURING+METHOD+THEREOF&rft.inventor=LU+JIECH-FUN&rft.inventor=WEN+CHI-YUAN&rft.inventor=HSUEH+CHE-HSIANG&rft.inventor=WU+MINGI&rft.inventor=YEH+YU-LUNG&rft.inventor=WU+JIAN&rft.inventor=FANG+CHUNIEH&rft.inventor=SU+CHINGUNG&rft.date=2017-07-06&rft.externalDBID=A1&rft.externalDocID=US2017194190A1