TEST PATTERNS FOR DETERMINING SIZING AND SPACING OF SUB-RESOLUTION ASSIST FEATURES (SRAFs)

A processor receives an integrated circuit design, divides the integrated circuit design into a test portion and a remaining portion, and adds sub-resolution assist features (SRAFs) having different size and spacing parameters to the test portion of the integrated circuit design to generate a single...

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Bibliographic Details
Main Authors Abdo Amr Y, Graur Ioana
Format Patent
LanguageEnglish
Published 06.07.2017
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A processor receives an integrated circuit design, divides the integrated circuit design into a test portion and a remaining portion, and adds sub-resolution assist features (SRAFs) having different size and spacing parameters to the test portion of the integrated circuit design to generate a single test pattern. Exposure and development equipment performs a single exposure and development process of the single test pattern to produce a single test photoresist. The processor analyzes the single test photoresist to determine which of the size and spacing parameters are unacceptable and which are acceptable, based on differences between the single test photoresist and a model photoresist that the test portion of the integrated circuit design without the SRAFs would produce. The processor adds SRAFs having the acceptable size and spacing parameters to the remaining portion of the integrated circuit design.
Bibliography:Application Number: US201514985686