MULTI-CORE COMMUNICATION ACCELERATION USING HARDWARE QUEUE DEVICE

Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache ("LLC"), and a har...

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Bibliographic Details
Main Authors Kenny Jonathan, Burres Bradley A, Sonnier David, Herdrich Andrew J, Wilkinson Hugh, Burroughs William, Clee James T, Bernstein Debra, Van Doren Stephen R, Yan An, Vangati Narender, Tsai Jr-Shian, Ma Te K, Tai Tsung-Yuan C, Wang Ren, Whitesell Jamison D, Cunningham Andrew, Pirog Jerry, Eads Gage, Richardson Bruce, Venkatesan Namakkal N, Hasting Joseph R, McDonnell Niall D, Miller Stephen, Wang Yipeng, Verplanke Edwin
Format Patent
LanguageEnglish
Published 06.07.2017
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache ("LLC"), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.
Bibliography:Application Number: US201614987676