Protection Structure for Semiconductor Device Package

A chip stack having a protection structure for semiconductor device package, which comprises a first chip and a second chip stacked with each other, wherein said first chip has a first surface, said second chip has a second surface, said first surface and said second surface are two surfaces facing...

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Main Authors LIN REING, LIAO PEIUN, TING PO-WEI, LIN CHENG-KUO, CHANG YU-FAN, TSAI SHU-HSIAO, WU YU-KAI, CHIANG CHIH-FENG
Format Patent
LanguageEnglish
Published 08.06.2017
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
GYROSCOPIC INSTRUMENTS
MEASURING
MEASURING DISTANCES, LEVELS OR BEARINGS
MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICALDEVICES
MICROSTRUCTURAL TECHNOLOGY
NAVIGATION
PERFORMING OPERATIONS
PHOTOGRAMMETRY OR VIDEOGRAMMETRY
PHYSICS
SEMICONDUCTOR DEVICES
SURVEYING
TESTING
TRANSPORTING
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Summary:A chip stack having a protection structure for semiconductor device package, which comprises a first chip and a second chip stacked with each other, wherein said first chip has a first surface, said second chip has a second surface, said first surface and said second surface are two surfaces facing to each other, wherein at least one metal pillar is formed on at least one of said first surface and said second surface and connected with the other, at least one protection ring is formed on at least one of said first surface and said second surface and having a first gap with the other, and at least one electrical device is formed on at least one of said first surface and said second surface, wherein said at least one electrical device is located inside at least one of said at least one protection ring.
Bibliography:Application Number: US201615147401