ARRAY SUBSTRATE
An array substrate includes: a display area; a non-display area outside of the display area; a gate-in-panel (GIP) circuit in the non-display area; a plurality of clock signal lines in the non-display area and configured to transfer signals to the GIP circuit; and connection lines in the non-display...
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Main Authors | , |
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Format | Patent |
Language | English |
Published |
04.05.2017
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Subjects | |
Online Access | Get full text |
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Summary: | An array substrate includes: a display area; a non-display area outside of the display area; a gate-in-panel (GIP) circuit in the non-display area; a plurality of clock signal lines in the non-display area and configured to transfer signals to the GIP circuit; and connection lines in the non-display area and configured to connect the plurality of clock signal lines to the GIP circuit. Each of the plurality of clock signal lines is a ring shaped line. |
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Bibliography: | Application Number: US201615220911 |