GAP FILL SELF PLANARIZATION ON POST EPI

• Main Authors: Chen Po-Chang, Leu Po-Hsiung, Liu Ding-I
• Format: Patent
• Language: English
• Published: 23.03.2017
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

The present disclosure relates to an integrated chip having gate electrodes separated from an epitaxial source/drain region by gaps filled with a flowable dielectric material. In some embodiments, the integrated chip has an epitaxial source/drain region protruding outward from a substrate. A first gate structure, having a conductive gate electrode, is separated from the epitaxial source/drain region by a gap. A flowable dielectric material is disposed within the gap, and a pre-metal dielectric (PMD) layer is arranged above the flowable dielectric material. The PMD layer continuously extends between a sidewall of the first gate structure and a sidewall of a second gate structure, and has an upper surface that is substantially aligned with an upper surface of the conductive gate electrode. A metal contact is electrically coupled to the conductive gate electrode and is disposed within an inter-level dielectric layer over the PMD layer and the first gate structure.