MOSFET WITH ULTRA LOW DRAIN LEAKAGE
A semiconductor device includes a monocrystalline substrate configured to form a channel region between two recesses in the substrate. A gate conductor is formed on a passivation layer over the channel region. Dielectric pads are formed in a bottom of the recesses and configured to prevent leakage t...
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Main Authors | , , , |
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Format | Patent |
Language | English |
Published |
02.02.2017
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Subjects | |
Online Access | Get full text |
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Summary: | A semiconductor device includes a monocrystalline substrate configured to form a channel region between two recesses in the substrate. A gate conductor is formed on a passivation layer over the channel region. Dielectric pads are formed in a bottom of the recesses and configured to prevent leakage to the substrate. Source and drain regions are formed in the recesses on the dielectric pads from a deposited non-crystalline n-type material with the source and drain regions making contact with the channel region. |
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Bibliography: | Application Number: US201615292747 |