LOW RESISTANCE BITLINE AND SOURCELINE APPARATUS FOR IMPROVING READ AND WRITE OPERATIONS OF A NONVOLATILE MEMORY

Described is an apparatus for improving read and write margins. The apparatus comprises: a sourceline; a first bitline; a column of resistive memory cells, each resistive memory cell of the column coupled at one end to the sourceline and coupled to the first bitline at another end; and a second bitl...

Full description

Saved in:
Bibliographic Details
Main Authors Hamzaoglu Fatih, Wei Liqiong, Lin Blake C, Wang Yih, Dray Cyrille
Format Patent
LanguageEnglish
Published 19.01.2017
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
Online AccessGet full text

Cover

More Information
Summary:Described is an apparatus for improving read and write margins. The apparatus comprises: a sourceline; a first bitline; a column of resistive memory cells, each resistive memory cell of the column coupled at one end to the sourceline and coupled to the first bitline at another end; and a second bitline in parallel to the first bitline, the second bitline to decouple read and write operations on the bitline for the resistive memory cell. Described is also an apparatus which comprises: a sourceline; a bitline; a column of resistive memory cells, each resistive memory cell in the column coupled at one end to the sourceline and coupled to the bitline at another end; and sourceline write drivers coupled to the bitline and the sourceline, wherein the sourceline write drivers are distributed along the column of resistive memory cells.
Bibliography:Application Number: US201615280935