ADDER-SUBTRACTOR AND CONTROL METHOD THEREOF

An adder-subtractor includes a first XOR circuit that inverts or non-inverts data from a second input line; first and second operand registers that hold outputs of first and second input selector; a result register that holds the operation result in response to the clock; and an adder that outputs a...

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Bibliographic Details
Main Authors KAN RYUJI, KIMURA Kouji
Format Patent
LanguageEnglish
Published 01.12.2016
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:An adder-subtractor includes a first XOR circuit that inverts or non-inverts data from a second input line; first and second operand registers that hold outputs of first and second input selector; a result register that holds the operation result in response to the clock; and an adder that outputs an operation result of first and second input data in the first and second operand registers to the result register and also to inputs of the first and second input selectors via the first bypass line. The adder includes a second XOR circuit for the first and second input data, a carry calculation unit that calculates carry data of the first and second input data, a fourth XOR circuit that inverts or not an output of the second XOR circuit, and a third XOR circuit for outputs of the carry calculation unit and outputs the operation result.
Bibliography:Application Number: US201615093797