PRE-TEST POWER-OPTIMIZED BIN REASSIGNMENT FOLLOWING SELECTIVE VOLTAGE BINNING

Disclosed is a method wherein selective voltage binning and leakage power screening of integrated circuit (IC) chips are performed. Additionally, pre-test power-optimized bin reassignments are made on a chip-by-chip basis. Specifically, a leakage power measurement of an IC chip selected from a volta...

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Bibliographic Details
Main Authors Bickford Jeanne P, Arsovski Igor, Lichtensteiger Susan K, McMahon Robert J, Grzymkowski Paul J, Perry Troy J, Sopchak Thomas G, Picozzi David M
Format Patent
LanguageEnglish
Published 27.10.2016
Subjects
BASIC ELECTRIC ELEMENTS
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
SEMICONDUCTOR DEVICES
TESTING
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Summary:Disclosed is a method wherein selective voltage binning and leakage power screening of integrated circuit (IC) chips are performed. Additionally, pre-test power-optimized bin reassignments are made on a chip-by-chip basis. Specifically, a leakage power measurement of an IC chip selected from a voltage bin can is compared to a bin-specific leakage power screen value of the next slower voltage bin. If the leakage power measurement is higher, the IC chip will be left in the voltage bin to which it is currently assigned. If the leakage power measurement is lower, the IC chip will be reassigned to that next slower voltage bin. These processes can be iteratively repeated until no slower voltage bins are available or the IC chip cannot be reassigned. IC chips can subsequently be tested according to testing parameters, including the minimum test voltages, associated with the voltage bins to which they are finally assigned.
Bibliography:Application Number: US201514695112