INSTRUCTION AND LOGIC FOR MEMORY ACCESS IN A CLUSTERED WIDE-EXECUTION MACHINE

A processor includes a Level-2 (L2) cache, a first and second cluster of execution units, and a first and second data cache unit (DCU) communicatively coupled to the respective clusters of execution units and to the L2 cache. The DCUs each include a data cache and logic to receive a memory operation...

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Bibliographic Details
Main Authors LECHENKO Anton W, BABAYAN Boris A, IYER Jayesh, SHISHLOV Sergey Y, EFIMOV Andrey
Format Patent
LanguageEnglish
Published 20.10.2016
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A processor includes a Level-2 (L2) cache, a first and second cluster of execution units, and a first and second data cache unit (DCU) communicatively coupled to the respective clusters of execution units and to the L2 cache. The DCUs each include a data cache and logic to receive a memory operation from an execution unit, respond to the memory operation with information from the data cache when the information is available in the data cache, and retrieve the information from the L2 cache when the information is unavailable in the data cache. The processor further includes logic to maintain contents of the data cache of the first DCU as equal to contents of the data cache of the second DCU at all clock cycles of operation of the processor.
Bibliography:Application Number: US201315103795