SHARED CONTROL OF A PHASE LOCKED LOOP (PLL) FOR A MULTI-PORT PHYSICAL LAYER (PHY)

Methods and systems for shared control of a phase locked loop (PLL) for a multi-port physical layer (PHY) are disclosed. In one aspect, an arbitration logic circuit is coupled to ports of a multi-port PHY sharing a phase locked loop (PLL). Upon receiving an indication that the shared PLL is to be re...

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Bibliographic Details
Main Authors Barash Dror, Vilas Mark Wesley, Deans Russell Coleman, Winemiller Chad Everett
Format Patent
LanguageEnglish
Published 06.10.2016
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Methods and systems for shared control of a phase locked loop (PLL) for a multi-port physical layer (PHY) are disclosed. In one aspect, an arbitration logic circuit is coupled to ports of a multi-port PHY sharing a phase locked loop (PLL). Upon receiving an indication that the shared PLL is to be reset, the arbitration logic circuit commands the ports sharing the PLL to enter a state in which any reset of the shared PLL would have minimal or no effect in their operations. In this manner, an integrated circuit (IC) including a multi-port PHY may be configured with only one PLL and associated clock generating logic to provide a clock signal for some or all of its ports, thus reducing its semiconductor area and power consumption. Furthermore, the ports of the multi-port PHY may operate independently from each other obviating any configuration and/or interoperability problems associated with having a shared PLL.
Bibliography:Application Number: US201514679436