NOVEL PHASE LOCKED LOOP (PLL) ARCHITECTURE

• Main Authors: Arcudia Kenneth Luis, Shafer Jeffrey Andrew, Pandita Bupesh
• Format: Patent
• Language: English
• Published: 15.09.2016
• Subjects: BASIC ELECTRONIC CIRCUITRY; ELECTRIC COMMUNICATION TECHNIQUE; ELECTRICITY; GENERATION OF NOISE BY SUCH CIRCUITS; GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING,BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN ANON-SWITCHING MANNER; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION

In one embodiment, a phase locked loop (PLL) comprises a voltage-controlled oscillator (VCO), a frequency divider configured to frequency divide an output signal of the VCO to produce a feedback signal, and a phase detection circuit configured to detect a phase difference between a reference signal and the feedback signal, and to generate an output signal based on the detected phase difference. The PLL also comprises a proportional circuit configured to generate a control voltage based on the output signal of the phase detection circuit, wherein the control voltage tunes a first capacitance of the VCO to provide phase correction. The PLL further comprises an integration circuit configured to convert the control voltage into a digital signal, to integrate the digital signal, and to tune a second capacitance of the VCO based on the integrated digital signal to provide frequency tracking.