THREE DIMENSIONAL SELF-ALIGNMENT OF FLIP CHIP ASSEMBLY USING SOLDER SURFACE TENSION DURING SOLDER REFLOW

Techniques are provided for flip-chip assembly and packaging of microelectronic, photonics and optoelectronic devices in which three-dimensional alignment of package components is achieved using solder surface tension during a solder reflow process to move one or more package components and align su...

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Bibliographic Details
Main Authors Nah Jae-Woong, Martin Yves C, Barwicz Tymon
Format Patent
LanguageEnglish
Published 01.09.2016
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
OPTICAL ELEMENTS, SYSTEMS, OR APPARATUS
OPTICS
PHYSICS
SEMICONDUCTOR DEVICES
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Summary:Techniques are provided for flip-chip assembly and packaging of microelectronic, photonics and optoelectronic devices in which three-dimensional alignment of package components is achieved using solder surface tension during a solder reflow process to move one or more package components and align such components in X, Y and Z directions using mechanical stops and chip butting techniques.
Bibliography:Application Number: US201514634189