REDUCED EXTERNAL RESISTANCE FINFET DEVICE

The present invention relates generally to semiconductor devices, and more particularly, to a structure and method of reducing external resistance within fin field effect transistor (finFET) devices. A first spacer and a second spacer may be formed adjacent to a gate which may reduce capacitance in...

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Bibliographic Details
Main Authors PONOTH SHOM S, STANDAERT THEODORUS E, YAMASHITA TENKO, CHENG KANGGUO, SREENIVASAN RAGHAVASIMHAN
Format Patent
LanguageEnglish
Published 07.07.2016
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:The present invention relates generally to semiconductor devices, and more particularly, to a structure and method of reducing external resistance within fin field effect transistor (finFET) devices. A first spacer and a second spacer may be formed adjacent to a gate which may reduce capacitance in a substantial portion of a epitaxial source-drain region while also permitting a portion of the epitaxial source-drain region to be located close to a channel. By reducing capacitance from the gate on the substantial portion of the epitaxial source-drain region, resistance in the epitaxial source-drain region may be reduced which may result in increased device performance.
Bibliography:Application Number: US201514591041