GATE STRUCTURE INTEGRATION SCHEME FOR FIN FIELD EFFECT TRANSISTORS

In one embodiment, a semiconductor device is provided that includes a gate structure present on a channel portion of a fin structure. The gate structure includes a dielectric spacer contacting a sidewall of a gate dielectric and a gate conductor. Epitaxial source and drain regions are present on opp...

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Bibliographic Details
Main Authors TSENG CHIAHSUN, YIN YUNPENG, HE HONG, YEH CHUNN
Format Patent
LanguageEnglish
Published 28.04.2016
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Summary:In one embodiment, a semiconductor device is provided that includes a gate structure present on a channel portion of a fin structure. The gate structure includes a dielectric spacer contacting a sidewall of a gate dielectric and a gate conductor. Epitaxial source and drain regions are present on opposing sidewalls of the fin structure, wherein surfaces of the epitaxial source region and the epitaxial drain region that is in contact with the sidewalls of the fin structure are aligned with an outside surface of the dielectric spacer. In some embodiments, the dielectric spacer, the gate dielectric, and the gate conductor of the semiconductor device are formed using a single photoresist mask replacement gate sequence.
Bibliography:Application Number: US201514985711