NAND Flash Memory Integrated Circuits and Processes with Controlled Gate Height

A NAND flash memory integrated circuit chip includes a cell area and a peripheral area with structures of different heights, with higher structures in the peripheral area to provide low resistance and lower structures in the memory array so that the risk of word line collapse is maintained at accept...

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Bibliographic Details
Main Authors KOKETSU HIROAKI, FUJIKURA EIICHI, TOYAMA FUMIAKI, OKAZAKI SUSUMU, FUTASE TAKUYA
Format Patent
LanguageEnglish
Published 31.12.2015
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A NAND flash memory integrated circuit chip includes a cell area and a peripheral area with structures of different heights, with higher structures in the peripheral area to provide low resistance and lower structures in the memory array so that the risk of word line collapse is maintained at acceptable levels.
Bibliography:Application Number: US201414320103