APPARATUS AND METHOD FOR EFFICIENTLY IMPLEMENTING A PROCESSOR PIPELINE

Various different embodiments of the invention are described including: (1) a method and apparatus for intelligently allocating threads within a binary translation system; (2) data cache way prediction guided by binary translation code morphing software; (3) fast interpreter hardware support on the...

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Bibliographic Details
Main Authors HYUSEINOVA MIREM, TOPP JAROSLAW, XEKALAKIS POLYCHRONIS, NEELAKANTAM NAVEEN, KHARTIKOV DENIS M, PAVLOU DEMOS, FRYMAN JOSHUA B, KELM JOHN H, LAI PATRICK P, KEPPEL DAVID, KNIES ALLAN D, STELLPFLUG GREGOR, SCHUCHMAN ETHAN
Format Patent
LanguageEnglish
Published 31.12.2015
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Various different embodiments of the invention are described including: (1) a method and apparatus for intelligently allocating threads within a binary translation system; (2) data cache way prediction guided by binary translation code morphing software; (3) fast interpreter hardware support on the data-side; (4) out-of-order retirement; (5) decoupled load retirement in an atomic OOO processor; (6) handling transactional and atomic memory in an out-of-order binary translation based processor; and (7) speculative memory management in a binary translation based out of order processor.
Bibliography:Application Number: US201414319265