METHOD OF REDUCING LATENCY IN A FLEXIBLE PARSER AND AN APPARATUS THEREOF

• Main Authors: SCHMIDT GERALD, ANAND VISHAL, DANIEL TSAHI
• Format: Patent
• Language: English
• Published: 24.12.2015
• Subjects: ELECTRIC COMMUNICATION TECHNIQUE; ELECTRICITY; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION

Embodiments of the apparatus for reducing latency in a flexible parser relate to an implementation that optimizes each parser engine within the parser. A packet enters the parser. Each of the parser engines processes the packet if processing is required. Otherwise, the parser engine simply forwards the packet through without processing the packet, thereby reducing latency. Each parser engine includes a memory. The memory stores bypass data and status information that indicates whether parsing for this packet is completed and, thus, no further processing is required by subsequent parser engines. Each parser engine also includes a counter, which is incremented whenever a packet enters the parser engine and is decremented whenever a packet exists the parser engine. A packet bypasses the parser engine based on the counter of the parser engine and the status information of that packet.