DYNAMIC VIDEO CORE CLOCK AND VOLTAGE SCALING

• Main Authors: CHUNG HYUKJUNE, YEE SCOTT
• Format: Patent
• Language: English
• Published: 03.12.2015
• Subjects: CALCULATING; CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION ANDCOMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION ANDCOMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWNENERGY USE; COMPUTING; COUNTING; ELECTRIC COMMUNICATION TECHNIQUE; ELECTRIC DIGITAL DATA PROCESSING; ELECTRICITY; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; PHYSICS; PICTORIAL COMMUNICATION, e.g. TELEVISION; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS; TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINSTCLIMATE CHANGE

Disclosed are systems and methods for dynamically scaling a clock and/or voltage of a video core. The method may include buffering video frames in an input buffer queue and encoding the video frames from the input buffer queue with a video encoder to generate encoded video frames. An input buffer queue is monitored to generate an indication of a fullness of the buffer queue and a high input-threshold level is established for the input buffer queue and a low input-threshold level for the input buffer queue. A clock frequency of the video encoder is increased in response to the indication of the fullness reaching the high input-threshold for the buffer queue and the clock frequency of the video decoder is decreased in response to the indication of the fullness reaching the low input-threshold for the buffer queue.