CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME

• Main Authors: LIU TSANG-YU, CHANG SHU-MING, LEE PO-HAN
• Format: Patent
• Language: English
• Published: 15.10.2015
• Subjects: BASIC ELECTRIC ELEMENTS; CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION ORPROCESSING OF GOODS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; SEMICONDUCTOR DEVICES; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS; TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINSTCLIMATE CHANGE

A chip package includes semiconductor chips, inner spacers, cavities, conductive portions and solder balls. The semiconductor chip has at least an electronic component and at least an electrically conductive pad disposed on an upper surface thereof. The conductive pad is arranged abreast to one side of the electronic component and electrically connected thereto. The cavities open to a lower surface of the semiconductor chip and extend toward the upper surface to expose the conductive pad on the upper surface. The conductive portions fill the cavities from the lower surface and electrically connected the to conductive pad. The solder balls are disposed on the lower surface and electrically connected to the conductive portions. A gap is created between an outer wall of the inner spacers and an edge of the semiconductor chip.