Gate Formation Memory by Planarization

Semiconductor devices and methods of producing the devices are disclosed. The devices are formed by forming a gate structure on a substrate. The gate structure includes a charge trapping dielectric formed between the substrate and a first poly layer. A top dielectric is formed over the poly layer an...

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Bibliographic Details
Main Authors FANG SHENQING, RAMSBEY MARK T, MATSUMOTO DAVID, CHEN CHUN
Format Patent
LanguageEnglish
Published 25.06.2015
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:Semiconductor devices and methods of producing the devices are disclosed. The devices are formed by forming a gate structure on a substrate. The gate structure includes a charge trapping dielectric formed between the substrate and a first poly layer. A top dielectric is formed over the poly layer and a sidewall dielectric is formed on a side of the poly layer. A second poly layer is formed over the gate structure such that a portion of the second poly layer includes a vertical portion that is in contact with the sidewall dielectric and a top portion that is in contact with the top dielectric. The top portion of the second poly layer can then be removed through, for instance, planarization.
Bibliography:Application Number: US201314136358