FACILITATING CHIP DICING FOR METAL-METAL BONDING AND HYBRID WAFER BONDING

A method of forming a stacked assembly of semiconductor chips can include juxtaposing and metallurgically joining kerf metal elements exposed in kerf regions of a first wafer with corresponding kerf metal elements exposed in kerf regions of a second wafer, and affixing undiced semiconductor chips of...

Full description

Saved in:
Bibliographic Details
Main Authors LIN WEI, KALTALIOGLU ERDEM, WINSTEL KEVIN R, SKORDAS SPYRIDON, FAROOQ MUKTA G
Format Patent
LanguageEnglish
Published 04.06.2015
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online AccessGet full text

Cover

More Information
Summary:A method of forming a stacked assembly of semiconductor chips can include juxtaposing and metallurgically joining kerf metal elements exposed in kerf regions of a first wafer with corresponding kerf metal elements exposed in kerf regions of a second wafer, and affixing undiced semiconductor chips of the first wafer with corresponding undiced semiconductor chips of the second wafer. The assembled wafers are then cut along the dicing lanes thereof into a plurality of individual assemblies of stacked semiconductor chips, each assembly including an undiced semiconductor chip of the first wafer and an undiced semiconductor chip of the second wafer affixed therewith.
Bibliography:Application Number: US201314096325