APPARATUS FOR TIME DOMAIN OFFSET CANCELLATION TO IMPROVE SENSING MARGIN OF RESISTIVE MEMORIES
Described are apparatuses for time domain offset cancellation. One example of the apparatus includes: a variable resistance memory cell; a reference resistive memory cell; a detector to generate an output indicating timing relationship between a pulse arriving from the variable resistance memory cel...
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Main Authors | , |
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Format | Patent |
Language | English |
Published |
04.06.2015
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Subjects | |
Online Access | Get full text |
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Summary: | Described are apparatuses for time domain offset cancellation. One example of the apparatus includes: a variable resistance memory cell; a reference resistive memory cell; a detector to generate an output indicating timing relationship between a pulse arriving from the variable resistance memory cell and a pulse arriving from the reference resistive memory cell; and a logic unit to receive the output from the detector and to generate a control signal to the adjust timing relationship as indicated by the detector. |
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Bibliography: | Application Number: US201314094488 |