CONSTRAINING PREFETCH REQUESTS TO A PROCESSOR SOCKET

In an embodiment, a processor includes at least one core having one or more execution units, a first cache memory and a first cache control logic. The first cache control logic may be configured to generate a first prefetch request to prefetch first data, where this request is to be aborted if the f...

Full description

Saved in:
Bibliographic Details
Main Authors BAN KHUN, WILKERSON CHRISTOPHER B, CHUANG PENG-FEI, PUGSLEY SETH H, SCOTT ROBERT L, CHISHTI ZESHAN A, LU SHIH-LIEN L, CHOW KINGSUM
Format Patent
LanguageEnglish
Published 28.05.2015
Subjects
CALCULATING
CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION ANDCOMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION ANDCOMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWNENERGY USE
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS
INFORMATION STORAGE
PHYSICS
STATIC STORES
TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINSTCLIMATE CHANGE
Online AccessGet full text

Cover

More Information
Summary:In an embodiment, a processor includes at least one core having one or more execution units, a first cache memory and a first cache control logic. The first cache control logic may be configured to generate a first prefetch request to prefetch first data, where this request is to be aborted if the first data is not present in a second cache memory coupled to the first cache memory. Other embodiments are described and claimed.
Bibliography:Application Number: US201314090056