LAYER ARRANGEMENT AND A WAFER LEVEL PACKAGE COMPRISING THE LAYER ARRANGEMENT
The invention relates to a layer arrangement and a wafer level package comprising the layer arrangement, and in particular, the layer arrangement comprises a getter layer and further comprises a sacrificial layer. The wafer level package may be used in microelectromechanical systems (MEMS) packaging...
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Format | Patent |
Language | English |
Published |
14.05.2015
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Online Access | Get full text |
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Abstract | The invention relates to a layer arrangement and a wafer level package comprising the layer arrangement, and in particular, the layer arrangement comprises a getter layer and further comprises a sacrificial layer. The wafer level package may be used in microelectromechanical systems (MEMS) packaging at a vacuum level of about 10 mTorr or less such as close to 1 mTorr (i.e. MEMS vacuum packaging). |
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AbstractList | The invention relates to a layer arrangement and a wafer level package comprising the layer arrangement, and in particular, the layer arrangement comprises a getter layer and further comprises a sacrificial layer. The wafer level package may be used in microelectromechanical systems (MEMS) packaging at a vacuum level of about 10 mTorr or less such as close to 1 mTorr (i.e. MEMS vacuum packaging). |
Author | XIE LING NAGARAJAN RANGANATHAN CHEN BANGTAO CHIDAMBARAM VIVEK HO BENG YEUNG |
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Snippet | The invention relates to a layer arrangement and a wafer level package comprising the layer arrangement, and in particular, the layer arrangement comprises a... |
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SubjectTerms | ALLOYS BASIC ELECTRIC ELEMENTS CHEMISTRY ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY FERROUS OR NON-FERROUS ALLOYS METALLURGY MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICALDEVICES MICROSTRUCTURAL TECHNOLOGY PERFORMING OPERATIONS PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTUREOR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS SEMICONDUCTOR DEVICES TRANSPORTING TREATMENT OF ALLOYS OR NON-FERROUS METALS |
Title | LAYER ARRANGEMENT AND A WAFER LEVEL PACKAGE COMPRISING THE LAYER ARRANGEMENT |
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