LAYER ARRANGEMENT AND A WAFER LEVEL PACKAGE COMPRISING THE LAYER ARRANGEMENT

The invention relates to a layer arrangement and a wafer level package comprising the layer arrangement, and in particular, the layer arrangement comprises a getter layer and further comprises a sacrificial layer. The wafer level package may be used in microelectromechanical systems (MEMS) packaging...

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Bibliographic Details
Main Authors NAGARAJAN RANGANATHAN, HO BENG YEUNG, XIE LING, CHIDAMBARAM VIVEK, CHEN BANGTAO
Format Patent
LanguageEnglish
Published 14.05.2015
Subjects
ALLOYS
BASIC ELECTRIC ELEMENTS
CHEMISTRY
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
FERROUS OR NON-FERROUS ALLOYS
METALLURGY
MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICALDEVICES
MICROSTRUCTURAL TECHNOLOGY
PERFORMING OPERATIONS
PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTUREOR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
SEMICONDUCTOR DEVICES
TRANSPORTING
TREATMENT OF ALLOYS OR NON-FERROUS METALS
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Summary:The invention relates to a layer arrangement and a wafer level package comprising the layer arrangement, and in particular, the layer arrangement comprises a getter layer and further comprises a sacrificial layer. The wafer level package may be used in microelectromechanical systems (MEMS) packaging at a vacuum level of about 10 mTorr or less such as close to 1 mTorr (i.e. MEMS vacuum packaging).
Bibliography:Application Number: US201314372015