MECHANISMS FOR PREVENTING LEAKAGE CURRENTS IN MEMORY CELLS

Memory cells and operation methods thereof are provided. A memory device includes a number of memory cells. Each of the memory cells includes a first transistor, a switch and a capacitor. The first transistor has a drain connected to a corresponding bit-line. The switch has a first terminal connecte...

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Bibliographic Details
Main Authors TSUI FELIX YING-KIT, CHEN SHIH-HSIEN, KO CHUN-YAO, LU HAU-YAN, KUO LIANG-TAI
Format Patent
LanguageEnglish
Published 09.04.2015
Subjects
ELECTRICITY
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:Memory cells and operation methods thereof are provided. A memory device includes a number of memory cells. Each of the memory cells includes a first transistor, a switch and a capacitor. The first transistor has a drain connected to a corresponding bit-line. The switch has a first terminal connected to a source of the first transistor and a second terminal coupled to a reference voltage. The capacitor has a first plate and a second plate, and the first plate of the capacitor is electrically connected to a gate of the first transistor. The second plate of the capacitor is connected to a corresponding word line. The switch is turned off when the memory cell is not selected to perform a write operation or a read operation.
Bibliography:Application Number: US201314048873