SELECTIVE PASSIVATION OF VIAS

• Main Authors: CHENG TIEN-JEN, SIMON ANDREW H, XU YIHENG, ZHANG JOHN, KANE TERENCE L, RADENS CARL J, CLEVENGER LAWRENCE A, WANG YUN-YU
• Format: Patent
• Language: English
• Published: 19.03.2015
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A method of forming an integrated circuit structure includes forming a cap layer above a first ILD layer of a first metal level, the first ILD layer includes a recess filled with a first conductive material to form a first interconnect structure. Next, a second ILD layer is formed above the cap layer and a via is formed within the second ILD layer as a second interconnect structure of a second metal level. The via is aligned with the first interconnect structure. Subsequently, a portion of the cap layer is removed to extend the via to expose a top portion of the first conductive material then a passivation cap is selectively formed at a bottom portion of the via in the second ILD layer and the passivation cap contacting the top portion of the first conductive material. The passivation cap includes a metal alloy to form an interface between the bottom portion of the via and the first conductive material.