VCSEL Packaging

A process to bond VCSEL arrays to submounts and printed circuit boards is provided. The process is particularly suited to large area thin and ultra-thin VCSEL arrays susceptible to bending and warping. The process integrates a flatness measurement step and applying appropriate combination of pressur...

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Bibliographic Details
Main Authors SEURIN JEAN-FRANCOIS, GHOSH CHUNI LAL, WATKINS LAURENCE, WANG QING
Format Patent
LanguageEnglish
Published 12.03.2015
Subjects
BASIC ELECTRIC ELEMENTS
CLADDING OR PLATING BY SOLDERING OR WELDING
CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING
DEVICES USING STIMULATED EMISSION
ELECTRICITY
MACHINE TOOLS
METAL-WORKING NOT OTHERWISE PROVIDED FOR
PERFORMING OPERATIONS
SOLDERING OR UNSOLDERING
TRANSPORTING
WELDING
WORKING BY LASER BEAM
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Summary:A process to bond VCSEL arrays to submounts and printed circuit boards is provided. The process is particularly suited to large area thin and ultra-thin VCSEL arrays susceptible to bending and warping. The process integrates a flatness measurement step and applying appropriate combination of pressure prior to bonding the VCSEL array to the submount or a printed circuit using a vacuum flux-less bonding process. The process is very promising in making very good quality bonding between the VCSEL array and a submount or a printed circuit board. The process is applied to construct optical modules with improved flatness that may be integrated with other electronic components in constructing optoelectronic systems.
Bibliography:Application Number: US201414479325