CLOCK TREE IN CIRCUIT AND OPERATION METHOD THEREOF

A clock tree in a circuit and an operation method thereof are provided. The clock tree includes at least two sub clock trees, at least two voltage-controllable power-mode-aware (PMA) buffers and a power-mode control circuit. The PMA buffers delay a system clock to serve as the delayed clock, and pro...

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Bibliographic Details
Main Authors CHANG SHIHIEH, CHOU CHUNG-HAN, HUANG SHIH-HSU, NIEH YOW-TYNG
Format Patent
LanguageEnglish
Published 22.01.2015
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A clock tree in a circuit and an operation method thereof are provided. The clock tree includes at least two sub clock trees, at least two voltage-controllable power-mode-aware (PMA) buffers and a power-mode control circuit. The PMA buffers delay a system clock to serve as the delayed clock, and provide respectively the delayed clock to the sub clock trees. The power-mode control circuit provides at least two first power information to at least two function modules respectively, wherein a power mode of each of the function modules is determined according to the first power information respectively. The power-mode control circuit provides at least two second power information to the PMA buffers respectively, wherein a delay time of each of the PMA buffers is determined according to the second power information respectively.
Bibliography:Application Number: US201414509055