METHODS FOR FORMING INTEGRATED CIRCUITS WITH REDUCED REPLACEMENT METAL GATE HEIGHT VARIABILITY

Methods for fabricating integrated circuits with reduced replacement metal gate height variability are provided. In an embodiment, a method includes providing a semiconductor substrate with a fin supported thereon and forming a conformal material layer overlying the fin and the semiconductor substra...

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Bibliographic Details
Main Authors TREVINO KRISTINA, LIU YUAN-HUNG, MAENG CHANG HO, HAN TAEJOON, WELLS GABRIEL PADRON
Format Patent
LanguageEnglish
Published 22.01.2015
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:Methods for fabricating integrated circuits with reduced replacement metal gate height variability are provided. In an embodiment, a method includes providing a semiconductor substrate with a fin supported thereon and forming a conformal material layer overlying the fin and the semiconductor substrate. A trench is etched within the conformal material layer such that the trench exposes a surface of the fin and the semiconductor substrate. A conductive gate structure is formed within the trench, the conformal material layer is removed, and spacers are formed on the sidewalls of the conductive gate.
Bibliography:Application Number: US201313943909