PARALLELIZING COMPILE METHOD, PARALLELIZING COMPILER, PARALLELIZING COMPILE APPARATUS, AND ONBOARD APPARATUS

A parallelizing compile method includes, dividing a sequential program for an embedded system into multiple macro tasks, specifying (i) a starting end task and (ii) a termination end task, fusing (i) the starting end task, (ii) the termination end task, and (iii) a group of the multiple macro tasks,...

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Main Authors UMEDA DAN, KIMURA KEIJI, MORI HIROSHI, TANI MITSUHIRO, KASAHARA HIRONORI, MIKAMI HIROKI, KANEHAGI YOHEI, HAYASHI AKIHIRO
Format Patent
LanguageEnglish
Published 18.12.2014
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A parallelizing compile method includes, dividing a sequential program for an embedded system into multiple macro tasks, specifying (i) a starting end task and (ii) a termination end task, fusing (i) the starting end task, (ii) the termination end task, and (iii) a group of the multiple macro tasks, extracting a group of multiple new macro tasks from the multiple new macro tasks fused in the fusing based on a data dependency, performing a static scheduling assigning the multiple new macro tasks to the multiple processor units, so that the group of the multiple new macro tasks is parallelly executable by the multiple processor units, and generating a parallelizing program. In addition, a parallelizing compiler, a parallelizing compile apparatus and an onboard apparatus are provided.
Bibliography:Application Number: US201414302886