VOLTAGE-CONTROLLABLE POWER-MODE-AWARE CLOCK TREE, AND SYNTHESIS METHOD AND OPERATION METHOD THEREOF

A voltage-controllable power-mode-aware (PMA) clock tree in an integrated circuit (IC) and a synthesis method and an operation method thereof are provided. The PMA clock tree includes at least two sub clock trees, at least two PMA buffers and a power mode control circuit. The at least two PMA buffer...

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Bibliographic Details
Main Authors CHANG SHIHIEH, CHOU CHUNG-HAN, HUANG SHIH-HSU, NIEH YOW-TYNG
Format Patent
LanguageEnglish
Published 27.11.2014
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A voltage-controllable power-mode-aware (PMA) clock tree in an integrated circuit (IC) and a synthesis method and an operation method thereof are provided. The PMA clock tree includes at least two sub clock trees, at least two PMA buffers and a power mode control circuit. The at least two PMA buffers respectively delay a system clock and provide the delayed system clock to the sub clock trees as delayed clocks. The power mode control circuit respectively provides at least two first power information to at least two function modules to respectively determine the power modes of the function modules. The power mode control circuit respectively provides at least two second power information to the at least two PMA buffers to respectively determine the delay time of the PMA buffers.
Bibliography:Application Number: US201314019546