METHOD, APPARATUS, AND SYSTEM FOR IMPROVING INTER-CHIP AND SINGLE-WIRE COMMUNICATION FOR A SERIAL INTERFACE
A system and method consistent with the present disclosure includes a master device, bus interface link, and slave device. The master device includes a power supply and a detection unit to detect an impedance of the power supply. The inverter provides a first path to the power supply on a first stag...
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Main Author | |
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Format | Patent |
Language | English |
Published |
18.09.2014
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Subjects | |
Online Access | Get full text |
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Summary: | A system and method consistent with the present disclosure includes a master device, bus interface link, and slave device. The master device includes a power supply and a detection unit to detect an impedance of the power supply. The inverter provides a first path to the power supply on a first stage of a clock signal and. Further, the inverter provides a second path to a first ground line on a second stage of a clock signal. The bus interface link couples the master device to a slave device. Additionally, a bi-directional communications line is coupled to the bus interface link. A gating component provides a second ground line to the power supply through the first path. Furthermore, a receiver determines bit values from a plurality of clock data signals transmitted from the master device. |
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Bibliography: | Application Number: US201313840885 |