PROCESS FOR FILLING VIAS IN THE MICROELECTRONICS

A process for metalizing a through silicon via feature in a semiconductor integrated circuit device, the process including, during the filling cycle, reversing the polarity of circuit for an interval to generate an anodic potential at said metalizing substrate and desorb leveler from the copper surf...

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Main Authors LIN XUAN, ANTONELLIS THEODORE, SHAO WENBO, WANG CHEN, PANECCASIO, JR. VINCENT, WANG CAI, RICHARDSON THOMAS B, ABYS JOSEPH A
Format Patent
LanguageEnglish
Published 01.05.2014
Subjects
APPARATUS THEREFOR
BASIC ELECTRIC ELEMENTS
CHEMISTRY
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
ELECTROFORMING
ELECTROLYTIC OR ELECTROPHORETIC PROCESSES
METALLURGY
PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTIONOF COATINGS
SEMICONDUCTOR DEVICES
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Summary:A process for metalizing a through silicon via feature in a semiconductor integrated circuit device, the process including, during the filling cycle, reversing the polarity of circuit for an interval to generate an anodic potential at said metalizing substrate and desorb leveler from the copper surface within the via, followed by resuming copper deposition by re-establishing the surface of the copper within the via as the cathode in the circuit, thereby yielding a copper filled via feature.
Bibliography:Application Number: US201213981974