TECHNIQUE FOR PRESERVING CACHED INFORMATION DURING A LOW POWER MODE

A technique to retain cached information during a low power mode, according to at least one embodiment. In one embodiment, information stored in a processor's local cache is saved to a shared cache before the processor is placed into a low power mode, such that other processors may access infor...

Full description

Saved in:
Bibliographic Details
Main Authors GEORGE VARGHESE, ALLAREY JOSE, JAHAGIRDAR SANJEEV
Format Patent
LanguageEnglish
Published 24.04.2014
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online AccessGet full text

Cover

More Information
Summary:A technique to retain cached information during a low power mode, according to at least one embodiment. In one embodiment, information stored in a processor's local cache is saved to a shared cache before the processor is placed into a low power mode, such that other processors may access information from the shared cache instead of causing the low power mode processor to return from the low power mode to service an access to its local cache.
Bibliography:Application Number: US201314141926