HIGH SPEED SERIAL PERIPHERAL INTERFACE SYSTEM

A serial peripheral interface (SPI) system including a bus adapter is disclosed. The bus adapter may include a data converter that may be adapted to receive respective first and second data from a first master output peripheral input (MOPI) line and a chip select line from a SPI master device. The d...

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Bibliographic Details
Main Authors VANDERLINDEN STEVEN L, REMIS LUKE D, DECESARIS MICHAEL, SELLMAN GREGORY D
Format Patent
LanguageEnglish
Published 24.04.2014
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A serial peripheral interface (SPI) system including a bus adapter is disclosed. The bus adapter may include a data converter that may be adapted to receive respective first and second data from a first master output peripheral input (MOPI) line and a chip select line from a SPI master device. The data converter may also be adapted to interleave the first and second data, and the data converter may be adapted to transmit the interleaved first and second data synchronously with a second clock signal on a second MOPI line. The bus adapter may also include a clock rate adjuster adapted to generate the second clock signal to transmit to a SPI peripheral device. The second clock signal may be adapted to enable the SPI peripheral device to read the transmitted data.
Bibliography:Application Number: US201213657501