METHODOLOGY ON DEVELOPING METAL FILL AS LIBRARY DEVICE
A methodology for developing metal fill as a library device and, in particular, a method of generating a model of the effects (e.g., capacitance) of metal fills in an integrated circuit and a design structure is disclosed. The method is implemented on a computing device and includes generating a mod...
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Main Authors | , |
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Format | Patent |
Language | English |
Published |
27.02.2014
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Subjects | |
Online Access | Get full text |
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Summary: | A methodology for developing metal fill as a library device and, in particular, a method of generating a model of the effects (e.g., capacitance) of metal fills in an integrated circuit and a design structure is disclosed. The method is implemented on a computing device and includes generating a model for effects of metal fill in an integrated circuit. The metal fill model is generated prior to completion of a layout design for the integrated circuit. |
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Bibliography: | Application Number: US201314068524 |