CHECKPOINTED BUFFER FOR RE-ENTRY FROM RUNAHEAD

Embodiments related to re-dispatching an instruction selected for re-execution from a buffer upon a microprocessor re-entering a particular execution location after runahead are provided. In one example, a microprocessor is provided. The example microprocessor includes fetch logic, one or more execu...

Full description

Saved in:
Bibliographic Details
Main Authors ROZAS GUILLERMO J, VANDERSCHOOT HENS, BOGGS DARRELL, SERRIS PAUL, RAMAKRISHNAN SRIDHARAN, EKMAN MAGNUS, HOYT BRAD, SEGELKEN ROSS
Format Patent
LanguageEnglish
Published 07.11.2013
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online AccessGet full text

Cover

More Information
Summary:Embodiments related to re-dispatching an instruction selected for re-execution from a buffer upon a microprocessor re-entering a particular execution location after runahead are provided. In one example, a microprocessor is provided. The example microprocessor includes fetch logic, one or more execution mechanisms for executing a retrieved instruction provided by the fetch logic, and scheduler logic for scheduling the retrieved instruction for execution. The example scheduler logic includes a buffer for storing the retrieved instruction and one or more additional instructions, the scheduler logic being configured, upon the microprocessor re-entering at a particular execution location after runahead, to re-dispatch, from the buffer, an instruction that has been previously dispatched to one of the execution mechanisms.
Bibliography:Application Number: US201213463627