SYSTEM AND METHOD FOR MULTI-STAGE TIME-DIVISION MULTIPLEXED LDPC DECODER

A low density parity check decoder includes a decoding process divided into two or more processing stages arranged in series. At one time, each processing stage processes a different code block than each other processing stage in the series. The decoder is capable of simultaneously decoding as many...

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Bibliographic Details
Main Author HENIGE THOMAS MICHAEL
Format Patent
LanguageEnglish
Published 17.10.2013
Subjects
BASIC ELECTRONIC CIRCUITRY
CODE CONVERSION IN GENERAL
CODING
DECODING
ELECTRICITY
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Summary:A low density parity check decoder includes a decoding process divided into two or more processing stages arranged in series. At one time, each processing stage processes a different code block than each other processing stage in the series. The decoder is capable of simultaneously decoding as many code blocks as stages. A controller passes the code blocks between the processing stages at the proper time and in the proper sequence. The controller passes the code blocks through the series of stages in a time-division multiplexed fashion.
Bibliography:Application Number: US201313787342