PROVIDING A FEEDBACK LOOP IN A LOW LATENCY SERIAL INTERCONNECT ARCHITECTURE

In one embodiment, the present invention includes a de-serializer to receive serial data at a first rate and to output a parallel data frame corresponding to the serial data aligned to a frame alignment boundary in response to a phase control signal received from a feedback loop coupled between the...

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Bibliographic Details
Main Authors SHOOR EHUD, LAZAR DROR, BENHAMOU ASSAF
Format Patent
LanguageEnglish
Published 19.09.2013
Subjects
BASIC ELECTRONIC CIRCUITRY
CODE CONVERSION IN GENERAL
CODING
DECODING
ELECTRICITY
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Summary:In one embodiment, the present invention includes a de-serializer to receive serial data at a first rate and to output a parallel data frame corresponding to the serial data aligned to a frame alignment boundary in response to a phase control signal received from a feedback loop coupled between the de-serializer and a receiver logic coupled to an output of the de-serializer. Other embodiments are described and claimed.
Bibliography:Application Number: US201313781039