NON-SELF ALIGNED NON-VOLATILE MEMORY STRUCTURE

A non-self aligned non-volatile memory structure includes a semiconductor substrate; a first gate insulation layer on said semiconductor substrate; a floating gate on first gate insulation layer; two doped regions in said semiconductor substrate, which are respectively on two sides of said first gat...

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Bibliographic Details
Main Authors HUANG WEN CHIEN, LIN HSIN CHANG, FAN YA-TING
Format Patent
LanguageEnglish
Published 18.07.2013
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A non-self aligned non-volatile memory structure includes a semiconductor substrate; a first gate insulation layer on said semiconductor substrate; a floating gate on first gate insulation layer; two doped regions in said semiconductor substrate, which are respectively on two sides of said first gate insulation layer, and adjoining said first gate insulation layer; a second gate insulation layer on said floating gate; and a control gate on said second gate insulation layer. Width of said control gate on said floating gate is less than that of said floating gate, and width of said control gate not on said floating gate is equal to or greater than width of said floating gate. Through the two non-self aligned gates, the non-volatile memory does not need to meet the requirement of gate line-to-line alignment, thus reducing complexity and cost of manufacturing process.
Bibliography:Application Number: US201213351319