ANNEAL TO MINIMIZE LEAKAGE CURRENT IN DRAM CAPACITOR

A method for forming a DRAM MIM capacitor stack comprises forming a first electrode layer, annealing the first electrode layer, forming a dielectric layer on the first electrode layer, annealing the dielectric layer, forming a second electrode layer on the dielectric layer, annealing the second elec...

Full description

Saved in:
Bibliographic Details
Main Authors DEWEERD WIM, ODE HIROYUKI
Format Patent
LanguageEnglish
Published 16.05.2013
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online AccessGet full text

Cover

More Information
Summary:A method for forming a DRAM MIM capacitor stack comprises forming a first electrode layer, annealing the first electrode layer, forming a dielectric layer on the first electrode layer, annealing the dielectric layer, forming a second electrode layer on the dielectric layer, annealing the second electrode layer, patterning the capacitor stack, and annealing the capacitor stack for times greater than about 10 minutes, and advantageously greater than about 1 hour, at low temperatures (less than about 300 C) in an atmosphere containing less than about 25% oxygen and preferably less than about 10% oxygen.
Bibliography:Application Number: US201113295292